ADCCLKSUSPEND0=PRSWUDIS, EM23WUCONVERT=WUDVL, ADCCLKSUSPEND1=PRSWUDIS, HSCLKRATE=DIV1, WARMUPMODE=NORMAL, DBGHALT=NORMAL
Control
| EM23WUCONVERT | EM23 Wakeup on Conversion 0 (WUDVL): When using suspend mode, conversions performed in EM2 or EM3 should not wake up the DMA until the FIFO’s DVL setting is reached. This saves more power for large OSR settings or infrequent sampling. 1 (WUCONVERT): When using suspend mode, conversions performed in EM2 or EM3 will wake up the DMA and keep it awake until the conversions are done, regardless of the DVL setting. This mode burns more power, but it is useful when the conversion rate is faster than the time for the DMA to cycle through wake up and going back to sleep as it converts more than 4 scan table entries. Without using the wake up on conversion mode, the FIFO may overflow while the DMA is going in and out of sleep. |
| ADCCLKSUSPEND0 | ADC_CLK Suspend - PRS0 0 (PRSWUDIS): Normal mode which does not disable the ADC_CLK. 1 (PRSWUEN): ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. |
| ADCCLKSUSPEND1 | ADC_CLK Suspend - PRS1 0 (PRSWUDIS): Normal mode which does not disable the ADC_CLK. 1 (PRSWUEN): ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. |
| DBGHALT | Debug Halt 0 (NORMAL): Continue operation as normal during debug mode 1 (HALT): Complete the current conversion and then halt during debug mode |
| WARMUPMODE | Warmup Mode 0 (NORMAL): Shut down the IADC after conversions have completed. 1 (KEEPINSTANDBY): Switch to standby mode after conversions have completed. The next warmup time will require 1us. 2 (KEEPWARM): Keep IADC fully powered after conversions have completed. |
| TIMEBASE | Time Base |
| HSCLKRATE | High Speed Clock Rate 0 (DIV1): Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less. 1 (DIV2): Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 2 (DIV3): Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 3 (DIV4): Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. |